View P10C68-45_4110388.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

P10C68/P11C68
PRELIMINARY INFORMATION
DS3600-1.2 September 1992
P10C68/P11C68
(Previously PNC10C68 and PNC11C68)
CMOS/SNOS NVSRAM HIGH PERFORMANCE 8 K x 8 NON-VOLATILE STATIC RAM
(Supersedes DS3159-1.3, DS3160-1.3, DS3234-1.1, DS3235-1.1)
The P10C68 and P11C68 are fast static RAMs (35 and 45 ns) with a non-volatile electically-erasable PROM (EEPROM) cell incorporating in each static memory cell. The SRAM can be read and written an unlimited number of times while independent non-volatile data resides in PROM. On the P10C68 data may easily be transferred from the SRAM to the EEPROM (STORE) and from the EEPROM back to the SRAM ( RECALL) using the NE (bar) pin. The Store and Recall cycles are initiated through software sequences on the P11C68. These devices combine the high performance and ease of use of a fast SRAM with the data integrity of nonvolatility. The P10C68 and P11C68 feature the industry standard pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and ceramic dual-in-line packages.
NE A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W NC A8 A9 A 11 G A 10 E DQ 7 DQ 6 DQ 5 DQ 4 DQ 3
FEATURES I Non-Volatile Data Integrity I 10 year Data Retention in EEPROM I 35ns and 45ns Address and Chip Enable Access Times I 20ns and 25ns Output Enable Access I Unlimited Read and Write to SRAM I Unlimited Recall Cycles from EEPROM I 104 Store Cycles to EEPROM I Automatic Recall on Power up I Automatic Store Timing I Hardware Store Protection I Single 5V 10% Operation I Available in Standard Package 28-pin 0.3-inch DIL plastic and ceramic I Commercial and Industrial temperature ranges ORDERING INFORMATION (See back page)
Figure 1. Pin connections - top view.
Pin Name A0 - A12 W DQ0 - DQ7 E G VCC VSS Pin 1 NE Pin 1 N/C
Function Address inputs Write enable Data in/out Chip enable Output enable Power (+5V) Ground Non volatile enable P10C68 No connection P11C68
1
P10C68/P11C68
EEPROM ARRAY 256 x 256 A3 A4 A5 A6 A7 A8 A9 A12 R O W D E C O D E R STATIC RAM ARRAY 256 x 256
STORE
RECALL
STORE/ RECALL CONTROL
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I N P U T B U F F E R S
COLUMN I/O COLUMN DECODER
A0
A1
A2
A10 A11
G NE (P10C68 only) E W
Figure 2. Logic block diagram.
2
P10C68/P11C68
ABSOLUTE MAXIMUM RATINGS Voltage on typical input relative to VSS Voltage on DQ0-7 and G(bar) Temperature under Bias Storage temperature Power dissipation DC output current -0.6V to 7.0V -0.5V to (Vcc + 0.5V) -55C to + 125C -65C to + 150C 1W 15mA NOTE Stresses greater than those listed in the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at any other conditions than those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect reliability.
(one output at a time, one second duration)
DC OPERATING CONDITIONS
Parameter Symbol Min. Supply voltage Input logic '1' voltage Input logic '0' voltage Ambient operating temperature commercial industrial VCC VIH VIL Tamb Tamb Value Typ. 5.0 2.2 VSS -0.5 0 -40 VCC +0.5 0.8 +70 +85 Max. V V V
o o
Units
Conditions
All inputs All inputs
C C
DC ELECTRICAL CHARACTERISTICS Commercial temperature range
Test conditions (unless otherwise stated): Tamb = 0C to 70C, Vcc = +5V (See notes 1, 2 and 3) Characteristic Symbol Min. Average power supply current Average power supply current during STORE cycle Average power supply current (standby, cycling TTL input levels) ICC1 ICC2 ISB1 Value Max. 75 65 50 mA mA mA tAVAV = 35ns tAVAV = 45ns All inputs at VIN 0.2V tAVAV = 35ns tAVAV = 45ns E(bar) VIH, all other inputs cycling E (bar)(VCC -0.2V), all other inputs at VIN0.2V or (VCC 0.2V) VCC = max, VIN = VSS to VCC VCC = max, VIN = VSS to VCC IOUT = 4mA IOUT = 8mA Units Conditions
23 20
mA mA
Average power supply current (standby, stable CMOS input levels)
ISB2
1
mA
Input leakage current (any input) Off state output leakage current Output logic '1' voltage Output voltage '0' voltage
IILK IOLK VOH VOL
1 5 2.4 0.4
A A V V
NOTES 1. ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 2. Bringing E (bar) VIH will not produce standby currents levels until any non-volatile cycle in progress has timed out. See Mode Selection table. 3. ICC2 is the average current required for the duration of the STORE cycle (tSTORE) after the sequence that initiates the cycle.
3
P10C68/P11C68
Industrial temperature range
Test conditions (unless otherwise stated): Tamb = -40C to 70C, Vcc = +5V 10% (See notes 4, 5 and 6) Characteristic Symbol Min. Average power supply current Average power supply current during STORE cycle Average power supply current (standby, cycling TTL input levels) ICC1 ICC2 ISB1 Value Max. 80 75 50 mA mA mA tAVAV = 35ns tAVAV = 45ns All inputs at VIN 0.2V tAVAV = 35ns tAVAV = 45ns E(bar) VIH, all other inputs cycling E (bar)(VCC -0.2V), all other inputs at VIN0.2V or (VCC 0.2V) VCC = max, VIN = VSS to VCC VCC = max, VIN = VSS to VCC IOUT = 4mA IOUT = 8mA Units Conditions
27 23
mA mA
Average power supply current (standby, stable CMOS input levels)
ISB2
1
mA
Input leakage current (any input) Off state output leakage current Output logic '1' voltage Output voltage '0' voltage
IILK IOLK VOH VOL
1 5 2.4 0.4
A A V V
NOTES 4. ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. 5. Bringing E (bar) VIH will not produce standby currents levels until any non-volatile cycle in progress has timed out. See Mode Selection table. 6. ICC2 is the average current required for the duration of the STORE cycle (tSTORE) after the sequence that initiates the cycle.
AC TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing reference levels Output load VSS to 3V 5ns 1.5V See Figure 3
5.0V 480 Ohms
CAPACITANCE Tamb = 25C, f = 1.0MHz (see note 7)
Parameter Input capacitance Output capacitance Symbol CIN COUT Max. Units 5 7 pF pF Conditions V=0 to 3V V=0 to 3V
OUTPUT 255 Ohms 30p INCLUDING SCOPE AND FIXTURE
NOTE 7. These parameters are characterised but not 100% tested.
Figure 3. AC output loading.
4
P10C68/P11C68
SRAM MEMORY OPERATION
Test conditions (unless otherwise stated): Commercial and Industrial Temperature Range Tamb = -40C to + 85C, Vcc = + 5V 10%
READ CYCLES 1 AND 2 (See note 8)
Symbol Standard tELQV tAVAV tAVQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL tWHQV Alternative tACS tRC tAA tOE tOH tLZ tOHZ tOLZ tHZ tPA tPS tWR Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Outout disable to output inactive Chip enable to power active Chip disable to power standby Write recovery time P10C68-35 P11C68-35 Min. Max. 35 35 35 20 5 5 20 0 15 0 25 45 0 25 55 0 20 5 5 25 45 45 25 P10C68-45 P11C68-45 Max. Min. 45
Parameter
Units
Notes
ns ns ns ns ns ns ns ns ns ns ns ns
9 10
11 11 12 12
NOTES 8. E (bar), G (bar) and W (bar) must make the transition between VIH(min) to VIL(max), or VIL(max) to VIH(min) in a monotonic fashion. NE (bar) must be VIH during entire cycle. 9. For READ CYCLE 1 and 2, W (bar) and NE (bar) must be high for entire cycle. 10. Device is continuously selected with E (bar) low, and G (bar) low. 11. Measured 200mV from steady state output voltage. Load capacitance is 5pF. 12. Parameter guaranteed but not tested.
tAVAV ADDRESS tAVQV tAXQX DQ (DATA OUT) DATA VALID
W
tWHQV
Figure 4. READ CYCLE 1 timing diagram (see notes 9 and 10).
5
P10C68/P11C68
tAVAV ADDRESS tELQV E tELQX tEHQZ G DQ (DATA OUT) ACTIVE ICC STANDBY tELICCH tGLQV tGHQZ DATA VALID tEHICCL
tGLQX
W
tWHQV
Figure 5. READ CYCLE 2 timing diagram (see note 9).
WRITE CYCLE 1 : W (BAR) CONTROLLED (See notes 8 and 13) Commercial and Industrial Temperature Range
Symbol Standard tAVAV tWLWH tELWH tDVWH tWHDX tAVWH tAVWL tWHAX tWLQZ tWHQZ Alternative tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Write cycle time Write pulse width Chip enable to end of write Data set-up to end of write Data hold after end of write Address set-up to end of write Address set-up to start of write Address hold after end of write Write enable to output disable Output active after end of write Parameter P10C68-35 P11C68-35 Max. Min. 45 35 35 30 0 35 0 0 35 5 5 P10C68-45 P11C68-45 Max. Min. 45 35 35 30 0 35 0 0 35 Units Notes
ns ns ns ns ns ns ns ns ns ns
11, 14
NOTES 13. E (bar) or W (bar) must be VIH during address transitions. 14. If W (bar) is low when E (bar) goes low, the outputs remain in the high impedance state.
6
P10C68/P11C68
tAVAV ADDRESS tELWH E tAVWL W tDVWH DATA IN DATA VALID tWLQZ DATA OUT PREVIOUS DATA HIGH IMPEDANCE tWHQX tWHDX tAVWH tWLWH tWHAX
Figure 6. WRITE CYCLE 1: W (bar) controlled timing diagram (see notes 8 and 13).
WRITE CYCLE 2 : E (BAR) CONTROLLED (See notes 8 and 13)
Symbol Standard tAVAV tWLEH tELEH tDVEH tEHDX tAVEH tEHAX tAVWL Alternative tWC tWP tCW tDW tDH tAW tWR tAS Write cycle time Write pulse width Chip enable to end of write Data set-up to end of write Data hold after end of write Address set-up to end of write Address hold after end of write Address set-up to start of write P10C68-35 P11C68-35 Max. Min. 45 35 35 30 0 35 0 0 P10C68-45 P11C68-45 Max. Min. 45 35 35 30 0 35 0 0
Parameter
Units
Notes
ns ns ns ns ns ns ns ns
tAVAV ADDRESS tAVEL E tAVEH W tWLEH tDVEH DATA IN DATA VALID tEHDX tELEH tEHAX
DATA OUT
HIGH IMPEDANCE
Figure 7. WRITE CYCLE 2: E (bar) controlled timing diagram (see notes 8 and 13).
7
P10C68/P11C68
VCC 5.0V 3.3V
t
AUTO RECALL
STORE INHIBIT
Figure 8. Automatic RECALL and STORE inhibit.
NON-VOLATILE MEMORY OPERATION OF P10C68 MODE SELECTION
E H L L L L L L W X H L H L L H G X L X L H L H NE X H H L L L X Not selected Read RAM Write RAM Non-volatile recall (Note 15) Non-volatile store No operation Mode Power Standby Active Active Active ICC2 Active
NOTE 15. An automatic RECALL also takes place on chip power-up, starting when Vcc exceeds 3.3V, and taking tRECALL from the time at which Vcc exceeds 3.3V. Vcc must not drop below 3.3V once it has exceeded it for the RECALL to function properly.
STORE CYCLE 1 : W (BAR) CONTROLLED (See note 16)
Symbol Standard tWLQX tGHNL tNLWL tWLNH tELWL Alternative tSTORE tWC Store cycle time Output disable set-up to NE (bar) fall Non-volatile set-up to write low Write low to NE (bar) rise Chip enable SET-UP Parameter P10C68-35 Min. Max. 10 0 0 45 0 0 0 45 0 P10C68-45 Min. Max. 10 ms ns ns ns ns 17 Units Notes
18
8
P10C68/P11C68
STORE CYCLE 2 : E (BAR) CONTROLLED (See note 13)
Symbol Standard tELQX1 tNLEL tWLEL tELNH tGHEL Alternative tSTORE tWC Store cycle time NE (bar) set-up to chip enable Write enable wet-up to chip enable Chip enable to NE (bar) rise Output disable set-up to E (bar) fall Parameter P10C68-35 Min. Max. 10 0 0 45 0 0 0 45 0 P10C68-45 Min. Max. 10 ms ns ns ns ns 17 Units Notes
18
NOTES 16. E (bar), G (bar), NE (bar) and W (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a monotonic fashion. 17. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Note that store cycles are inhibited/aborted by Vcc <3.3V (STORE inhibit). 18. Once twc has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the store cycle is completed automatically, ignoring all inputs. Any of NE (bar), G (bar), W (bar) or E (bar) may be used to terminate the store initiation cycle.
NE
G
tGHNL
tNLWL
tWLNH
W tELWL E tWLQX DQ (DATA OUT) HIGH IMPEDANCE
Figure 9. STORE CYCLE 1: W (bar) controlled timing diagram (see note 16).
tNLEL NE
G
tGHEL tWLEL
W
E
tELNH
tELQX1 DQ (DATA OUT) HIGH IMPEDANCE
Figure 10. STORE CYCLE 2: E (bar) controlled timing diagram (see note 16).
9
P10C68/P11C68
P10C68 RECALL CYCLE 1 : NE (BAR) CONTROLLED (See note 16)
Symbol Standard tNLQX tNLNH tGLNL tWHNL tELNL tNLQZ Alternative tRECALL tRC Recall cycle time Recall initiation cycle time Output enable set-up Write enable set-up Chip enable set-up NE (bar) fall to output inactive P10C68-35 Parameter Min. Max. 20 25 0 0 0 25 25 0 0 0 25 Min. Max. 20 s s ns ns ns ns 19 20 P10C68-45 Units Notes
P10C68 RECALL CYCLE 2 : E (BAR) CONTROLLED (See note 16)
Symbol Standard tELQX2 tELNH tNLEL tGLEL tWHEL Alternative tRECALL tRC Recall cycle time Recall initiation cycle time NE (bar) set-up Output enable set-up Write enable set-up P10C68-35 Parameter Min. Max. 20 25 0 0 0 25 0 0 0 P10C68-45 Min. Max. 20 s ns ns ns ns 19 20 Units Notes
P10C68 RECALL CYCLE 3 : G (BAR) CONTROLLED (See note 16)
Symbol Standard tGLQX2 tGLNH tNLGL tWHGL tELGL Alternative tRECALL tRC Recall cycle time Recall initiation cycle time NE (bar) set-up Write enable set-up Chip enable set-up P10C68-35 Parameter Min. Max. 20 25 0 0 0 25 0 0 0 P10C68-45 Min. Max. 20 s ns ns ns ns 19 20 Units Notes
NOTES 19. Measured with W (bar) and NE (bar) both returned high, and G (bar) returned low. Address transitions may not occur on any address pin during this time. 20. Once tRC has been satisfied by NE (bar), G (bar), W (bar) and E (bar) the RECALL cycle is completed automatically. Any of NE (bar), G (bar) or E (bar) may be used to terminate the RECALL initiation cycle.
10
P10C68/P11C68
tNLHN NE tGLNL G
W
tWHNL
E tELNL tNLQZ DQ (DATA OUT) HIGH IMPEDANCE tNLQX
Figure 11. P10C68 RECALL CYCLE 1: NE (bar) controlled timing diagram (see note 16).
tNLEL NE tGLEL G
W tWHEL E tELQX2 DQ (DATA OUT) HIGH IMPEDANCE tELNH
Figure 12. P10C68 RECALL CYCLE 2: E (bar) controlled timing diagram (see note 16).
tNLGL NE tGLNH
G tWHGL
W tELGL E tGLQX2 DQ (DATA OUT) HIGH IMPEDANCE
Figure 13. P10C68 RECALL CYCLE 3: E (bar) controlled timing diagram (see note 16).
11
P10C68/P11C68
NON-VOLATILE MEMORY OPERATION OF P11C68 MODE SELECTION
E H L L L W X H L H A12-A0 (hex) X X X 0000 1555 0AAA 1FFF 10F0 0F0F L H 0000 1555 0AAA 1FFF 10F0 0F0E Mode Not selected Read RAM Write RAM Read RAM Read RAM Read RAM Read RAM Read RAM Non-volatile STORE Read RAM Read RAM Read RAM Read RAM Read RAM Non-volatile RECALL I/O Output High Z Output data Input Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z ICC2 Active Power Standby Active Active Active 21, 22 21, 22 21, 22 21, 22 21, 22 20 21, 22 21, 22 21, 22 21, 22 21, 22 21 22 Notes
NOTES 21. The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W (bar) must be high during all six consecutive cycles. See STORE CYCLE and RECALL CYCLE tables and diagrams for further details. 22. I/O state assumes that G (bar) VIL. Activation of non-volatile cycles does not depend on the state of G (bar).
STORE / RECALL CYCLES 1 AND 2 (See notes 24 and 29)
Symbol Standard tAVAV tAXAV tAVQZ tAVEL tELEH tEHAX Alternative tACS tSKEW tELQZ tSTORE tRECALL tAE tEP tEA Read cycle time Skew between sequentially adjacent addresses Address valid to output inactive Store cycle time Recall cycle time Address set-up to chip enable Chip enable pulse width Chip disable to address change Parameter P11C68-35 Min. 35 5 75 10 20 0 35 0 0 45 0 Max. P11C68-45 Units Min. 45 5 75 10 20 Max. ns ns ns ms s ns ns ns Notes
23 25 26 26, 30 27 27 27
NOTES 23. Skew spec may be avoided by using E (bar) (STORE/RECALL CYCLE 2). 24. W (bar) VIH during entire address sequence to initiate a non-volatile cycle. Required address sequences are shown in the Mode Selection table. 25. Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. 26. Measured with W (bar) high, G (bar) low and E (bar) low. Note that STORE cycles (but not RECALLS) are aborted by Vcc < 3.3V (STORE Inhibit). 27. E (bar) must make the transition between VIH(max) to VIL(max), or VIL(max) to VIH(min) in a monotonic fashion. 28. Chip is continuously selected with E (bar) low. 29. Addresses 1 through 6 are found in the Mode Selection table. Address 6 determines whether the P11C68 performs a STORE or RECALL. A RECALL cycle is performed automatically at power up when VCC exceeds 3.3V. VCC must not drop below 3.3V once it has exceeded it for the RECALL to function properly, tRECALL is measured from the point at which VCC exceeds 3.3V. 30. Address transitions may not occur on any address pin during this time.
12
P10C68/P11C68
tSKEW
ADDRESS INVALID
tAVAV
ADDRESS 1
tAVAV
ADDRESS 2
tAVAV
ADDRESS 6
tSTORE / t RECALL tAVQZ
DQ (DATA OUT) DATA VALID DATA VALID DATA VALID HIGH IMPEDANCE DATA VALID
Figure 14. STORE/RECALL cycle 1. Address controlled timing diagram (see notes 22, 26 and 27).
tAVAV
ADDRESS ADDRESS 1
tAVAV
ADDRESS 6
tAVEL
E
tELEH
tEHAX
tSTORE / t RECALL
tELQZ
DQ (DATA OUT) DATA VALID DATA VALID HIGH IMPEDANCE DATA VALID
Figure 15. STORE/RECALL cycle 2. E (bar) controlled timing diagram (see notes 22, 25 and 27).
OPERATING NOTES
Note: References to NE (bar) should be taken as applying to P10C68 only and can be ignored for P11C68. The devices have two separate modes of operation: SRAM mode and non-volatile mode. In SRAM mode, the memory operates as an ordinary static RAM. While in non-volatile mode, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. SRAM READ The devices perform a read cycle when ever E (bar) and G (bar) are LOW and NE (bar) and W (bar) are HIGH. The address specified by the thirteen address pins A0-12 determine which of the 8192 data bytes will be accessed. When the READ is initiated by an address transistion, the outputs will be valid after a delay of tAVQV (READ CYCLE 1).
If the READ is initiated by E (bar) or G (bar), the outputs will be valid at tELQV or tGLQV, whichever is later. (READ CYCLE 2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins and will remain valid until another address change or until E (bar) or G (bar) is brought HIGH or W (bar) or NE (bar) is brought LOW. SRAM WRITE A write cycle is performed whenever E (bar) and W (bar) are LOW and NE (bar) is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E (bar) or W (bar) go HIGH at the end of the cycle. The data on the eight pins DQ0-7, will be written into the memory location specified by the address inputs if valid tDVWH before the end of a W (bar) controlled WRITE or tDVEH before the end of an E (bar) controlled WRITE.
13
P10C68/P11C68
It is recommended that G (bar) be kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G (bar) is left LOW, internal circuitry will turn off the output buffers tWHQZ after W (bar) goes LOW. Non-Volatile STORE - P10C68 A STORE cycle is performed when NE, (bar) E (bar) and W (bar) are LOW and G (bar) is HIGH. While any sequence to achieve this state will initiate a STORE, only W(bar) initiation (STORE CYCLE 1) and E (bar) initiation (STORE CYCLE 2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During the STORE cycle, previous non-volatile data is erased and the SRAM contents are then programmed into non-volatile elements. Once a STORE cycle is initiated, further input and output is disabled and the DQ0-7 pins are tri-stated until the cycle is completed. If E (bar) and G (bar) are LOW and W (bar) and NE (bar) are HIGH at the end of the cycle, a READ will be performed and the outputs will go active, signalling the end of the STORE. The P10C68 will not be activated into either a STORE or RECALL cycle by the software sequence required for the P11C68. Hardware Protect - P10C68 The P10C68 offers two levels of protection to suppress inadvertent STORE cycles. If the clock signals remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE will be initiated only after a HIGH to LOW transition on NE (bar)Because the STORE cycle is initiated by an NE (bar) transition, poweringup the chip with NE (bar) Low will not initiate a STORE cycle either. In addition to multi-trigger protection, the P10C68 offers hardware protection through Vcc Sense. A STORE cycle will not be initiated, and one in progress will discontinue, if Vcc goes below 3.3V. Non-Volatile RECALL - P10C68 A RECALL cycle is performed when E (bar), G (bar) and NE (bar) are LOW and W (bar) is HIGH. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take tNLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First the SRAM data is cleared and second, the non-volatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the non-volatile cells. The non-volatile data can be recalled an unlimited number of times. Address transitions may not occur during the RECALL cycle. Like the STORE cycle, a transition must occur on the NE (bar) pin to cause a RECALL, preventing inadvertent multi-triggering. On power-up, once Vcc exceeds Vcc sense voltage of 3.3V, a RECALL cycle is automatically initiated. The voltage on the Vcc pin must not drop below 3.3V once it has risen above it in order for the RECALL to operate properly. Due to the automatic RECALL, SRAM operation cannot commence until tNLQX after Vcc exceeds 3.3V. The P11C68 STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the P11C68 implements nonvolatile operation while remaining pin-for-pin compatible with standard 8Kx8 SRAMs. During the STORE cycle, an erase of the previous non-volatile data is first performed, followed by a program of the non-volatile elements. The program operation copies the SRAM data into non-volatile storage. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is critical that no invalid address states intervene in the sequence or the sequence will be aborted. The maximum skew between address inputs A0-12 for each address state is tSKEW (STORE CYCLE 1). If tSKEW is exceeded it is possible that the transitional data state will be interpreted as a valid address and the sequence will be aborted. If E (bar) controlled READ cycles are used for the sequence (STORE CYCLE 2), address skew is no longer a concern. To enable the STORE cycle the following READ sequence must be performed. 1. Read address 0000 (hex) Valid READ 2. Read address 1555 (hex) Valid READ 3. Read address 0AAA (hex) Valid READ 4. Read address 1FFF (hex) Valid READ 5. Read address 10F0 (hex) Valid READ 6. Read address 0F0F (hex) Initiate STORE Cycle Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G (bar) be LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. Once the first of the six reads has taken place, the read sequence must either complete or terminate with an incorrect address (other than 0000 hex) before it may be started anew. The P11C68 offers hardware protection against inadvertent STORE cycles through Vcc Sense. A STORE cycle will not be initiated, and one in progress will discontinue, if Vcc goes below 3.3V. A RECALL of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. Read address 0000 (hex) Valid READ 2. Read address 1555 (hex) Valid READ 3. Read address 0AAA (hex) Valid READ 4. Read address 1FFF (hex) Valid READ 5. Read address 10F0 (hex) Valid READ 6. Read address 0F0E (hex) Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second the non-volatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The non-volatile data can be recalled an unlimited number of times. Address transitions may not occur during the RECALL cycle.
14
P10C68/P11C68
On power-up, once Vcc exceeds the Vcc sense voltage of 3.3V, a RECALL cycle is automatically initiated. The voltage on the Vcc pin must not drop below 3.3V once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until tRECALL after Vcc exceeds 3.3V. The automatic RECALL feature can be adversely affected by factors such as supply rise time, temperature and elapsed time since the last STORE cycle. For this reason it is recommended that the user initiate a RECALL cycle after power-up for critical applications.
PACKAGE DETAILS
Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre.
PIN 1
7.620/8.128 (0.300/0.320)
1.27 (0.050) TYP
35.20/35.92 (1.386/1.414)
1.016/1.524 (0.040/0.060)
0.229/0.308 (0.009/0.012) 1.930/2.39 (0.05576/0.094) 0.36/0.51 (0.014/0.020) 2.54 (0.100) 7.37/7.87 (0.290/0.310)
3.30/4.06 (0.130/0.160)
Figure 16, 28-lead sidebrazed ceramic DIL (0.3in) DCB
1.37 (34.8)
PIN 1
Pin 1 Ref. notch
0.3/0.55 (0.76/1.4)
Leads
0.288 (7.32)
0.2 (5.08) max
SEATING PLANE
0.02 (0.51)
0.2/0.3 0.12 (3.05) min 0.015/0.02 (0.38/0.53) 0.1 (2.54) Nominal Centres 0.3 (7.62)
Figure 17. 28 plastic DIL Package (0.3in) DPB
15
P10C68/P11C68
ORDERING INFORMATION
PxxC68 - xx / xG / DxBS
Device number eg. 10 = hardware store/recall 11 = software store/recall Package type C = Ceramic P = Plastic Temperature range C = Commercial I = Industrial Speed Grade -35 = 35ns -45 = 45ns
HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Tx: 449637 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS Sequoia Research Park, 1500 Green Hills Road, Scotts Valley, California 95066, United States of America. Tel (408) 438 2900 ITT Telex: 4940840 Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES * FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Tx: 602858F Fax : (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Tx: 523980 Fax : (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 3296-0281 Fax: (03) 3296-0228 * NORTH AMERICA Integrated Circuits and Microwave Products, Scotts Valley, USA Tel (408) 438 2900 ITT Tx: 4940840 Fax: (408) 438 7023. Hybrid Products, Farmingdale, USA Tel (516) 293 8686 Fax: (516) 293 0061. * SOUTH EAST ASIA Singapore Tel: 2919291 Fax: 2916455 * SWEDEN Johanneshov Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * UNITED KINGDOM & SCANDINAVIA Swindon Tel: (0793) 518510 Tx: 444410 Fax : (0793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors Year Publication No. XX XXXX Issue No. X.X Month Year
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
16
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2001, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of P10C68-45

	To Download P10C68-45 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .